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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pD64084 three-dimensional y/c separation lsi with on-chip memory document no. s16021ej2v0ds00 (2nd edition) date published march 2003 ns cp (k) printed in japan data sheet 2 00 2 the mark shows major revised points. description the pD64084 realizes a high precision y/c separation by the three-dimension signal processing for ntsc signal. this product has the on-chip 4-mbit memory for flame delay, a high precision internal 10-bit a/d converter and d/a converter, and adapting 10-bit signal processing (only for luminance signal) and high picture quality. the pD64084 is completely single-chip system of 3d y/c separation. this lsi includes the wide clear vision id signal (japanese local format) decoder and id-1 signal decoder. features ? on-chip 4-mbit frame delay memory. ? 2 operation mode motion adaptive 3d y/c separation 2d y/c separation + frame recursive y/c nr ? embedded 10-bit a/d converter (1ch), 10-bit d/a converters (2ch), and system clock generator. ? embedded y coring, vertical enhancer, peaking filter, and noise detector. ? embedded id-1 signal decoder, and wcv-id signal decoder. ? i 2 c bus control. ? dual power supply of 2.5 v and 3.3 v. for digital : dv dd = 2.5 v for analog : av dd = 2.5 v for dram : dv ddram = 2.5 v for i/o : dv ddio = 3.3 v ordering information part number package pD64084gc-8ea-a note1 100-pin plastic lqfp (fine pitch) (14 14 mm) pD64084gc-8ea-y note2 100-pin plastic lqfp (fine pitch) (14 14 mm) notes 1. lead-free product 2. high-thermal-resistance product free datasheet http://www.0pdf.com
pD64084 2 data sheet s16021ej2v0ds pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14 mm) pD64084gc-8ea-a pD64084gc-8ea-y dgnd 1 2 3 4 testic1 5 testic2 6 test01 7 test02 8 test03 9 test04 10 test05 11 test06 12 test07 13 test08 14 test09 15 16 17 18 extaltf 19 extdyco0 20 extdyco1 21 extdyco2 22 extdyco3 23 extdyco4 24 extdyco5 25 extdyco6 26 extdyco7 27 extdyco8 28 extdyco9 29 dgndram 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 dgndram dgnd line altf dyco9 dyco8 dyco7 dyco6 dyco5 dyco4 dyco3 dyco2 dyco1 dyco0 dvdd nstd st1 st0 rstb clk8 ckmd avdd fsci fsco agnd agnd dvddram 32 dvddram 33 test10 34 test11 35 test12 test14 test15 test16 test17 36 37 38 dvddio 39 test13 40 dgnd 41 rpll 42 sla0 43 scl 44 sda 45 agnd 46 agnd dgnd agnd avdd 47 xi 48 xo 49 avdd 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dvdd dvdd test26 avdd avdd vrty vrby vcly ay i agnd agnd cbpy ayo aco cbpc vcomy kil csi test18 test19 test20 test21 test22 test23 test24 test25 free datasheet http://www.0pdf.com
pD64084 3 data sheet s16021ej2v0ds pin name aco : analog c (chroma) signal output agnd : analog section ground altf : alternate flag for digital yc output avdd : analog section power supply ayi : analog composite signal input ayo : analog y (luma) signal output cbpc : c-dac phase compensation output cbpy : y-dac phase compensation output ckmd : clock mode selection clk8 : 8f sc clock input / output csi : composite sync. input (active-low) dgnd : digital section ground dvdd : digital section power supply dvddio : digital i/o section power supply dvddram : internal dram section power supply dyco0 to dyco9 : digital yc signal (alternative) input / outputs extaltf : extend alternate flag for digital yc output extdyco0 to extdyco9 : extend digital yc signal (alternative) input / outputs fsci : f sc (subcarrier) input fsco : f sc (subcarrier) output kil : killer selection line : inter-line separate selection nstd : non standard detection monitor rpll : testing selection rstb : system reset (active-low) scl : serial clock input sda : serial data input / output sla0 : slave address selection st1, st0 : inner states monitor test01 to test26 : testing selection testic1, testic2 : ic testing section vcly : clamp voltage output for adc vrty : top voltage reference output for adc vrby : bottom voltage reference output for adc vcomy : common mode reference output for adc xi : x'tal input xo : x'tal output free datasheet http://www.0pdf.com
pD64084 4 data sheet s16021ej2v0ds block diagram 10-bit adc y/c separator & y noise reducer 3-line comb filter 10-bit c-dac c delay & c noise reducer 4-mbit frame memory wcv-id dec. id-1 dec. non-std. detector timing generator 4f sc i 2 c bus i/f power down cont. sync. separate ext. sync. separate 20 mhz comp. input 10-bit digital comp. input c output y output digital yc output i 2 c bus line f sc /227.5f h dec. 8-bit f sc dac 8f sc pll 4f sc c y 8f sc clamp bpf motion detector 3-line comb filter 3-line comb filter y-coring y-peaking y-enhancer id-1 enc. sel 10-bit y- d a c sel sel free datasheet http://www.0pdf.com
pD64084 5 data sheet s16021ej2v0ds terminology this manual use the abbreviation listed below: adc : a/d (analog to digital) converter dac : d/a (digital to analog) converter lpf : low-pass filter bpf : band-pass filter y signal, or luma : luminance, or luminance signal c signal, or chroma : color signal, or chrominance signal f sc : color subcarrier frequency = 3.579545 mhz 4f sc : 4 times f sc , burst locked clock = 14.318180 mhz 8f sc : 8 times f sc , burst locked clock = 28.636360 mhz f h : horizontal sync frequency = 15.734 khz 910f h : 910 times f h , line locked clock = 14.318180 mhz 1820f h : 1820 times f h , line locked clock = 28.636360 mhz f v : vertical sync frequency = 59.94 hz nr : noise reduction ynr : luminance (y) noise reduction cnr : chrominance (c) noise reduction wcv-id : wide clear vision standard id signal (japan only) id-1 : id signal of eiaj cpr-1204 in the following diagrams, a serial bus register is enclosed in a box: free datasheet http://www.0pdf.com
pD64084 6 data sheet s16021ej2v0ds contents 1. pin functions ................................................................................................................ .....................................9 1.1 pin functions ............................................................................................................... ...................................9 2. system overview .............................................................................................................. ..............................11 2.1 operation modes ............................................................................................................. .............................11 2.2 filter processing ........................................................................................................... ................................12 2.3 system delay................................................................................................................ ................................12 2.4 start-up of power supply and reset.......................................................................................... ...................13 3. video signal input block ..................................................................................................... .......................14 3.1 video signal inputs ......................................................................................................... ..............................14 3.2 pedestal level reproduction ................................................................................................. .......................14 3.3 video signal input level .................................................................................................... ...........................15 3.4 pin treatment............................................................................................................... .................................15 3.5 external adc connection method .............................................................................................. ..................16 4. clock/timing generation block................................................................................................ ...............17 4.1 sync separator and timing generator ......................................................................................... ................17 4.2 composite sync signal input................................................................................................. .......................17 4.3 horizontal/burst phase detection circuit.................................................................................... ..................17 4.4 pll filter circuit .......................................................................................................... .................................17 4.5 killer detection circuit.................................................................................................... ...............................17 4.6 f sc generator..................................................................................................................... ............................18 4.7 8f sc -pll circuit................................................................................................................... ..........................18 4.8 pin treatment............................................................................................................... .................................18 5. comb filter block ............................................................................................................ .............................19 5.1 line comb filter............................................................................................................ ................................19 5.2 frame comb filter ........................................................................................................... .............................19 5.3 mixer circuit ............................................................................................................... ...................................19 5.4 c signal subtraction ........................................................................................................ .............................19 6. motion detection block....................................................................................................... .......................20 6.1 line comb filter............................................................................................................ ................................20 6.2 dy detection circuit ........................................................................................................ ..............................20 6.3 dc detection circuit ........................................................................................................ .............................20 6.4 motion factor generation circuit ............................................................................................ ......................20 6.5 forcible control for the motion factor...................................................................................... ....................20 7. ynr/cnr block ................................................................................................................ .................................21 7.1 ynr/cnr processing.......................................................................................................... .........................21 7.2 nonlinear filter............................................................................................................ ..................................21 7.3 ynr/cnr operation stop...................................................................................................... .......................21 free datasheet http://www.0pdf.com
pD64084 7 data sheet s16021ej2v0ds 8. nonstandard signal detection block ........................................................................................... ...... 22 8.1 horizontal sync nonstandard signal detection................................................................................ ............ 22 8.2 vertical sync nonstandard signal detection .................................................................................. .............. 22 8.3 frame sync nonstandard signal detection..................................................................................... ............. 22 8.4 forced standard or nonstandard signal control............................................................................... ........... 22 8.5 noise level detection....................................................................................................... ............................ 22 9. wcv-id decoder / id-1 decoder block.......................................................................................... ........... 23 9.1 wcv-id decoder .............................................................................................................. ............................ 23 9.2 id-1 decoder ................................................................................................................ ................................ 24 10. y signal output processing block............................................................................................ ............ 25 10.1 y high-frequency coring circuit ........................................................................................... ...................... 25 10.2 y peaking filter circuit .................................................................................................. .............................. 26 10.3 vertical aperture compensation circuit .................................................................................... .................. 26 10.4 turning on/off y peaking and vertical aperture compensation ............................................................... .. 26 10.5 id-1 encoder .............................................................................................................. ................................. 26 11. c signal output processing block............................................................................................ ............ 27 11.1 c signal delay adjustment ................................................................................................. ......................... 27 11.2 bpf and gain processing ................................................................................................... ........................ 27 12. video signal output block................................................................................................... ..................... 28 12.1 digital yc output processing .............................................................................................. ........................ 28 12.2 video signal output level ................................................................................................. .......................... 28 12.3 pin treatment ............................................................................................................. ................................. 29 13. extend digital input / output............................................................................................... ..................... 30 13.1 usage of extend digital i/o terminals..................................................................................... ...................... 30 13.2 digital yc output format .................................................................................................. ............................ 30 13.3 pin treatment ............................................................................................................. ................................. 30 14. digital connection with ghost reducer ic pd64031a................................................................... 31 14.1 outline ................................................................................................................... ...................................... 31 14.2 system configuration and control method................................................................................... ............... 33 14.2.1 selecting video signal input path....................................................................................... ............... 33 14.2.2 selecting mode according to clock and video signal input path ....................................................... 33 14.3 setting of digital direct-connected system ................................................................................ ................ 34 14.3.1 hardware setting ........................................................................................................ ...................... 34 14.3.2 register setting ........................................................................................................ ........................ 35 15. i 2 c bus interface................................................................................................................ ............................. 36 15.1 basic specification ....................................................................................................... ............................... 36 15.2 data transfer formats ..................................................................................................... ............................ 37 15.3 initialization............................................................................................................ ...................................... 38 15.4 serial bus registers ...................................................................................................... .............................. 39 15.5 serial bus register functions ............................................................................................. ........................ 41 free datasheet http://www.0pdf.com
pD64084 8 data sheet s16021ej2v0ds 16. electrical characteristics .................................................................................................. ...................57 17. application circuit example ................................................................................................. ....................62 18. package drawing............................................................................................................. ...............................63 19. recommended soldering conditions............................................................................................ .........64 free datasheet http://www.0pdf.com
pD64084 9 data sheet s16021ej2v0ds 1. pin functions 1.1 pin functions table 1-1. pin functions (1/2) no. symbol i/o level buffer type pu/pd [k ? ] description 1, 33, 48, 75 dgnd - - - digital section ground 2, 3 testic1, testic2 i lvttl 3.3 v pd:50 ic testing (grounded) 4-12, 28-30, 78-85, 99 test01-test09, test10-test12, test18-test25, test26 - - - device test (open) 13 extaltf o lvttl 3.3 v 3 ma extended alternate flag output (this pin is enable in extdyco = 1) 14 - 23 extdyco0- extdyco9 i/o lvttl 3-state 3.3 v 3 ma extended digital i/o (these pins are enable in extdyco = 1) 24, 25 dgndram - - - dram section ground 26, 27 dvddram - - - dram section 2.5 v supply voltage 31 dvddio - - - i/o terminal section 3.3 v supply voltage 32, 40-43 test13, test14-test17 - - - device test (grounded) 34, 35 agnd - - - x?tal oscillation circuit section gound 36 xi i analog 2.5 v f sc generator reference clock input (x'tal is connected.) 37 xo o analog 2.5 v f sc generator reference clock inverted output (x'tal is connected.) 38 avdd - - - x?tal oscillation circuit section 2.5 v supply voltage 39, 62, 100 dvdd - - - digital section 2.5 v supply voltage 44 rpll i lvttl 3.3 v pd:50 test pin (grounded) 45 sla0 i lvttl 3.3 v i 2 c bus slave address selection input (l : b8h / b9h, h : bah / bbh) 46 scl i schmitt fail safe 3.3 v i 2 c bus clock input (connected to system scl line) 47 sda i/o schmitt fail safe 3.3 v 6 ma i 2 c bus data input/output (connected to system sda line) 49 agnd - - - f sc generator dac section ground 50 avdd - - - f sc generator dac section 2.5 v supply voltage 51 fsco o analog 2.5 v f sc generator f sc output 52, 53 agnd - - - 8f sc -pll ground 54 fsci i analog 2.5 v 8f sc -pll f sc input 55 avdd - - - 8f sc -pll section 2.5 v supply voltage 56 ckmd i lvttl 3.3 v pd:50 clock mode test input (grounded) ('l' : normal mode, 'h' : 8fsc clock external input mode) free datasheet http://www.0pdf.com
pD64084 10 data sheet s16021ej2v0ds table 1-1. pin functions (2/2) no. symbol i/o level buffer type pu/pd [k ? ] description 57 clk8 i/o lvttl 3-state 3.3 v 6 ma ckmd = 0 : 8f sc clock output ckmd = 1 : 8fsc clock input 58 rstb i schmitt 3.3 v pu:50 system reset input (active-low) (active-low reset pulse is input from the outside.) 59 st0 o lvttl 3.3 v 3 ma internal signal monitor output 0 60 st1 o lvttl 3.3 v 3 ma internal signal monitor output 1 61 nstd o lvttl 3.3 v 3 ma nonstandard signal detection monitor output ('l' : standard, 'h' : nonstandard) 63- 72 dyco0- dyco9 i/o lvttl 3-state 3.3 v 3 ma exadins=0: digital yc signal alternate output exadins=1: digital video data input for external adc (pull down unuse lower bit pins via resistor) dyco0 is the lsb, dyco9 is the msb. 73 altf o lvttl 3.3 v 3 ma exadins=0: digital yc signal alternate flag output ('l' : c, 'h' : y) exadins=1: 4f sc clock output for external adc 74 line i lvttl 3.3 v pd:50 forced inter-line processing selection input ('l' : ordinary processing, 'h' : forced inter-line processing) 76 kil i lvttl 3.3 v pd:50 external killer input ('l' : ordinary processing, 'h' : forced y/c separation stop) 77 csi i schmitt 3.3 v pu:50 composite sync input (active-low) 86 avdd - - - y-dac and c-dac 2.5 v supply voltage 87 cbpc o analog 2.5 v c-dac phase compensation output 88 aco o analog 2.5 v c-dac analog c signal output 89 ayo o analog 2.5 v y-dac analog y signal output 90 cbpy o analog 2.5 v y-dac phase compensation output 91 agnd - - - y-dac and c-dac ground 92 agnd - - - adc ground 93 ayi i analog 2.5 v adc analog composite signal input 94 vcly o analog 2.5 v adc clamp potential output 95 vrby o analog 2.5 v adc bottom reference voltage output 96 vrty o analog 2.5 v adc top reference voltage output 97 vcomy o analog 2.5 v adc common mode reference voltage 98 avdd - - - adc 2.5 v supply voltage free datasheet http://www.0pdf.com
pD64084 11 data sheet s16021ej2v0ds 2. system overview 2.1 operation modes the pD64084 can operate in the following major four signal processing modes. mode selection is performed according to nrmd on the serial bus. table 2-1. operation modes serial bus setting mode name function note pin input system clock feature model diagram nrmd = 0 ycs mode y/c separation ayi : composite signal burst locked clock (4f sc , 8f sc ) ? for standard signals, motion-adaptive three- dimensional y/c separation is performed. ? for nonstandard signals, inter-line y/c separation is performed. y c 4f sc ycs (3d/2d) comp. 4-mbit memory adc dac dac nrmd = 1 ycs+ mode 2d y/c separation and ycnr ayi : composite signal burst locked clock (4f sc , 8f sc ) ? inter-line y/c separation and frame recursive ynr and cnr is performed. y c dac ynr cnr dac adc 4f sc ycs (2d) comp. 4-mbit memory note 3d y/c separation, frame-recursive ynr/cnr, each function is independence. so these don't operate at the same time. free datasheet http://www.0pdf.com
pD64084 12 data sheet s16021ej2v0ds 2.2 filter processing table 2-2 lists filters used in each mode. table 2-2. filter matrix filter selected mode standard / nonstandard / killer signal detection effective-picture period blanking period still picture portion moving picture portion horizontal (11 s) ver tical (1h to 22h) ycs mode (nrmd = 0) standard signal detected frame comb line comb band-pass note nonstandard signal detected line comb band-pass note killer signal detected y output: through (y/c separation stop) c output: separated c signal ycs+ mode (nrmd = 1) standard or horizontal nonstandard signal detected line comb + frame recursive line comb band-pass note vertical nonstandard signal detected line comb band-pass note killer signal detected y output: through (y/c separation stop) c output: separated c signal vertical contour compensation / y peaking - active through note setting serial bus register sa09h: d0 (vflth) enables through output. 2.3 system delay the following diagram shows a model of system delays (video signal delays). figure 2-1. system delay model ayi adc ? 10 y-dac ? 1 c-dac ? 1 csi 0 1 ayo dyco9-2 aco y outpur c output c sync. input composite input 1h delay ? 910 delay ? 0~ ? 7 filter ? 4 ycs/ynr ? 21 cnr/delay ? 21 sa02h:d5 timing gen. cdl sa03h:d2-d0 exadins remark ? 1 corresponds to a one-clock pulse delay (4f sc or 910 f h = about 69.8 ns). free datasheet http://www.0pdf.com
pD64084 13 data sheet s16021ej2v0ds 2.4 start-up of power supply and reset it is necessary to reset the i 2 c bus interface immediately when it is supplied with power. when reset, the i 2 c bus interface releases its sda line and becomes operative. in addition, its write register is previously loaded with an initial value. <1> when the power is switched on, wait until the power supply line reaches and settles on a 3.3-v/2.5-v level before starting initialization. <2> initialize the i 2 c bus interface circuit by keeping the rstb pin at a low level for at least 10 s. <3> start communication on the i 2 c bus interface after 100 s from pull up the rstb pin to a high level. figure 2-2. i 2 c bus interface reset sequence dvddio rstb='l' 3.3 v start-up power on i 2 c bus access disable i 2 c bus access enable serial bus register data setting 3.3 v 0 v 2.5 v 0 v 3.3 v 0 v rstb='h' dvdd rstb 2.5 v start-up 3.3 v cut-off 2.5 v cut-off s min. 10 s min. 100 don't care caution reset is always necessary whether using the serial bus register or not. free datasheet http://www.0pdf.com
pD64084 14 data sheet s16021ej2v0ds 3. video signal input block this block converts analog video signals to digital form. figure 3-1. video signal input block diagram analog section supply voltage 2.5 v composite input (when the external adc used) composite input (when the internal adc used) clamp internal clamp pulse generator sampling clock clamp level feedback pedestal level error detection agnd avdd st0 altf vcly vrby vrty v in db 1 -db 8 pcl clk v rt v cl v rb 10-bit adc ( ? 10) clk 140 ire = 0.8 v p-p ay i 4f sc ,910f h 4f sc 8 2 1 0 10 10 100 ? 2 15 k ? 47 k ? 100 ? 8 dyco9-2 dyco1-0 f 1 pc659a f 10 to 47 f 0.1 f 0.1 f 0.1 f 0.1 vcomy f 0.1 10 exadins 256 st0s=01 3.1 video signal inputs the composite signal is input to the ayi pin. this analog video (composite) signal converts to digital video signal at internal 10-bit adc (exadins = 0). in case of external adc used, 10-bit composite signals in digital form are input to the dyco9 to dyco0 pins (exadins = 1). 3.2 pedestal level reproduction this circuit reproduces the pedestal level of a video signal. the pedestal level error detection circuit detects the difference between that level and the internal fixed value of 256 lsb levels, and outputs the feedback level. this output signal is connected to vcly pin via internal resistor to feed back to video signal for fixing pedestal level to 256 lsb. pull down the vcly pin via a 0.1 f bypass capacitor and a 10 to 47 f electrolysis capacitor for loop filter. caution in case of h-sync input level is bigger than 256lsb, this pedestal level also becomes over 256lsb. do not use this circuit when the external adc is used. free datasheet http://www.0pdf.com
pD64084 15 data sheet s16021ej2v0ds 3.3 video signal input level it is necessary to limit the level of video (composite) signal inputs to within a certain range to cope with the maximum amplitude of the video signal and variations in it. figure 3-2 shows the waveform of the video signal input whose amplitude is 140 ire p-p = 820 lsb (0.8 times a maximum input range of 1024 lsb). in this case, it is possible to input a white level of up to 131 ire for the y signal and up to 175 ire p-p for the c signal. figure 3-2. video signal input waveform example (for 75% color bar input) pedestal: 0 ire = 256 lsb sync-tip: ? 40 ire = 20 lsb 1.6 v ayi pin input 0.6 v + 131 ire 0 ire ? 43 ire 100 ire = 840 lsb 140 ire p-p = 0.8 1024 lsb = 820 lsb 1.00 v p-p 1023 896 768 640 512 384 256 128 0 dyco9-0 input / digital level (lsb) max. 131 ire = 1023 lsb remark the recommended input level of video signals is 140 ire p-p = 0.8 v p-p (1.00 v 0.8). 3.4 pin treatment ? supply 2.5 v to the avdd pins. isolate them sufficiently from the digital section power supply. ? use as wide wiring patterns as possible for the ground lines of each bypass capacitor and the agnd pins so as to minimize their impedance. ? connect a video signal to the ayi pin by capacitive coupling. maintain low input impedance for video signals. be sure to keep the wiring between the capacitor and the ayi pin as short as possible. ? pull down the vrty, vrby and vcomy reference voltage pins via a 0.1 f bypass capacitor. ? pull down the vcly pin via a 0.1 f bypass capacitor and a 10 to 47 f electrolysis capacitor. ? do not bring the digital system wiring (especially the memory system) close to this block and the straight downward of the ic. free datasheet http://www.0pdf.com
pD64084 16 data sheet s16021ej2v0ds 3.5 external adc connection method setting up exadins = 1 on the serial bus puts the ic in the external adc mode. in this mode, the altf pin is used to output 4f sc sampling clock pulses, and the dyco9 to dyco0 pins are used to receive digital data inputs. setting up st0s = 01 on the serial bus causes a clamp pulse to be output from the st0 pin. it is used as a pedestal clamp pulse for external adc. the clamp potential for the pedestal level of external adc must be determined so that the sampled value becomes about 256 8lsb. supply converted 10-bit data to the dyco9 to dyco0 pins via a 100 ? resistor. for using 8-bit adc (exp. pc659a), pull down the dyco1 and dyco0 pins via 100 ? resistor. in this mode, for adc in the pD64084, keep the vrty, vrby and vcomy pins open, and pull down the vcly and ayi pins via a 0.1 f capacitor. figure 3-3. example of application circuit set up for external adc clk over clamp bias msb: db 1 db 2 db 3 dgnd dv cc db 4 db 5 db 6 db 7 lsb: db 8 v rt (pin 1) altf (pin 73) dyco9 (pin 72): msb dyco8 (pin 71) dyco7 (pin 70) dyco6 (pin 69) dyco5 (pin 68) dyco4 (pin 67) dyco3 (pin 66) dyco1 (pin 64) dyco0 (pin 63) st0 (pin 59) dyco2 (pin 65): lsb nc av cc v in agnd pcl v cl av cc agnd v rb av cc agnd 140 ire = 0.8 v p-p 100 ? 10 10 ? 4f sc 5 v composite input clamp pulse 47 k ? : 1% 15 k ? : 1% pc659ags f 0.1 f 0.1 f 2.2 f 10 f 0.1 f 0.1 f 10 f 0.1 f 1 remark serial bus registers setting: exadins = 1, st0s = 01 free datasheet http://www.0pdf.com
pD64084 17 data sheet s16021ej2v0ds 4. clock/timing generation block this block generates system clock pulses and timing signals from video signals. figure 4-1. clock/timing generation block diagram dgnd agnd agnd avdd avdd 1/2 dvdd 22 to 33 pf 20 mhz,16 pf 22 to 33 pf dac xi fsci csi ayi adc composite input composite sync signal horizontal phase detection killer detection y/c separation stop, cnr stop system clock (4f sc , 910f h ) system clock (8f sc , 1820f h ) 2.5 v power supply voltage f sc bpf pll filter burst phase detection timing generator system timing f sc generator 8f sc pll sync. separator sync. separator xo fsco clk8 f 0.1 f 0.1 f 0.01 f 0.1 f 10 4.1 sync separator and timing generator these sections separate horizontal and vertical sync signals from the composite signal sampled at 4f sc or 910f h , and generate system timing signals by using them as references. 4.2 composite sync signal input an active-low composite sync signal separated from the video signal is input at the csi pin. this input is used as a reference signal to lock onto sync at the timing generator. 4.3 horizontal/burst phase detection circuit the horizontal phase detection circuit extracts the horizontal sync signal from the y signal sampled at 4f sc or 910f h to detect a horizontal phase error. this phase error is used for generation of 227.5f h and timing generator. the burst phase detection circuit extracts the burst signal from the composite signal sampled at 4f sc to detect a burst phase error. this phase error is used for f sc generation. 4.4 pll filter circuit the pll filter circuit integrates a burst or horizontal phase error to determine the oscillation frequency of the f sc generator ahead. 4.5 killer detection circuit the killer detection circuit compares the amplitude of the burst signal with the kilr value set on the serial bus to judge on a color killer. if the burst amplitude becomes smaller than or equal to the set kilr value when the burst locked clock is operating, the f sc generator is allowed to free-run. free datasheet http://www.0pdf.com
pD64084 18 data sheet s16021ej2v0ds 4.6 f sc generator the f sc generator generates f sc (or 227.5f h when the line locked clock is running) from an oscillation frequency determined in the pll filter. f sc is converted by internal dac to an analog sine waveform before it is output from the fsco pin. because this output contains harmonic components, they must be removed using an external band-pass filter (bpf) connected via a buffer, before the analog sine waveform is input to the fsci pin via a capacitor. the f sc generator uses a 20 mhz free-run clock pulse as a reference. 4.7 8f sc -pll circuit the 8f sc -pll circuit generates 8f sc (or 1820f h ) from f sc (or 227.5f h ) input at the fsci pin. the 8f sc signal is output from the clk8 pin. it is also used as the internal system clock. 4.8 pin treatment ? supply 2.5 v to the avdd pins. isolate them sufficiently from the digital section power supply. ? use as wide wiring patterns as possible for the ground lines of each bypass capacitor and the dgnd and agnd pins so as to minimize their impedance. ? connect a 20-mhz crystal resonator across the xi and xo pins. provide guard areas using ground patterns to keep these pins from interfering with other blocks. table 4-1 shows the crystal resonator specification example. ? connect a bpf to the fsco pin via an emitter follower. supply the f sc signal to the fsci pin via a capacitor. ? pull down the rpll pin via a 0 ? resistor. ? input an active-low composite sync signal to the csi pin. figure 4-2 shows the external composite sync separator application circuit example. table 4-1. crystal resonator specification example parameter specification frequency 20.000000 mhz load capacitance 16 pf equivalent serial resistance 40 ? or less frequency permitted tolerance 50 ppm or less frequency temperature tolerance 50 ppm or less figure 4-2. external composite sync separator application circuit example power supply (3.3 v) composite signal (1 v p-p ) composite sync. output 220 ? f 1 f 0.1 220 k ? 470 ? 22 k ? 2.2 k ? 1 k ? 4.7 k ? 1000 pf to 2200 pf free datasheet http://www.0pdf.com
pD64084 19 data sheet s16021ej2v0ds 5. comb filter block this block performs y/c separation or frame comb type ynr according to the result of checks in various detection circuits. figure 5-1. comb filter block diagram h h 0h c 2 c 3 c out y out h l h l 1h 2h 526h k 0 line comb filter frame memory composite input y signal output c signal output motion detection nonstandard signal detection killer detection h: killer signal detected h: nonstandard signal detected mixer circuit frame comb filter delay delay k =1 k 1 ? h h k line kil 5.1 line comb filter the c signal is separated from video signals that have been delayed by 0h, 1h, and 2h. this filter serves as a logical comb filter based on inter-line correlation to reduce dot and cross-color interference. the filter output (c 2 ) is used in the moving picture portion of standard signals, nonstandard signals, and blanking periods. 5.2 frame comb filter the c signal is separated from video signals that have been delayed by 1h and 526h. the filter output (c 3 ) is used in still picture portions by the motion detection circuit. 5.3 mixer circuit the mixer circuit mixes c signals to adapt to the motion according to the motion factor from the motion detection circuit. in other words, c out is generated by mixing the line comb filter output (c 2 ) and the frame comb filter output (c 3 ) by a mixture ratio according to the motion factor k (0 to 1). if the input signal is a nonstandard signal, or if the line pin is at a high level, c 2 is output without performing motion-adaptive mixture. 5.4 c signal subtraction the y out signal is separated by subtracting the c out signal from a composite video signal that has been delayed by 1h. subtraction is quitted when the killer detection circuit detects that the input signal is a color killer signal (monochrome signal or non-burst signal) or that the kil pin is at an 'h' level. free datasheet http://www.0pdf.com
pD64084 20 data sheet s16021ej2v0ds 6. motion detection block this block generates a 4-bit motion factor indicating an inter-frame motion level from the video signal inter-frame difference. this motion factor is used as a mixture ratio to indicate how the frame and line comb filter outputs are mixed. this block is used in the ycs mode. figure 6-1. motion detection block diagram c 2 c 1 y 2 y 1 4 0 0 lim lim | x | | x | | x | line comb filter (current frame) frame memory composite input to the mixer circuit md[3:0] dc detection circuit motion factor generation circuit maximum value section expansion circuit coring dc dy dy detection circuit lpf h h line comb filter (previous frame) h h | x | lpf dycor dccor gain gain dygain mss 0 dcgain coring f 0 mss 1 6.1 line comb filter before obtaining an inter-frame difference, the line comb filter performs y/c separation for the composite signals of both frames. 6.2 dy detection circuit the dy detection circuit detects a y signal inter-frame difference. after a y signal difference between the current and previous frames is obtained, its absolute value, obtained by limiting the frequency band for the y signal difference using an lpf, is output as a y frame difference signal, or a dy signal. 6.3 dc detection circuit the dc detection circuit detects a c signal inter-frame difference. after a c signal difference between the current and previous frames is obtained, its absolute value, obtained by limiting the frequency band for the c signal difference using an lpf, is output as a c frame difference signal, or a dc signal. because the phase of the c signal is inverted between frames, the absolute values of the c signals of both frames have been obtained before the difference is obtained. 6.4 motion factor generation circuit the motion factor generation circuit generates a 4-bit motion factor from the dy and dc signals. the first coring circuit performs coring according to the dycor and dccor settings on the serial bus to block weak signals like noise. the gain adjustment circuits ahead perform gain adjustment according to the dygain and dcgain settings on the serial bus to specify the sensitivity of the motion factor. these outputs are limited to a 4-bit width, and one having a higher level is selected for output by the maximum value selection circuit. the selected signal is expanded horizontally, then output as a final motion factor. 6.5 forcible control for the motion factor the motion factor can be set to 0 (forced stop) or a maximum value (forced motion) using the mss signal on the serial bus. free datasheet http://www.0pdf.com
pD64084 21 data sheet s16021ej2v0ds 7. ynr/cnr block this block performs frame recursive ynr and cnr. it is used in the ycs+ mode. figure 7-1. ynr/cnr block diagram ? y ? c frame memory y signal input c signal input y signal output c signal output cnr nonlinear filter ynr nonlinear filter killer signal detected current c current y substraction of noise component previous frame y previous frame c ynr/cnr stop signal frame difference frame difference ? y' ? c' noise component noise component delay delay demodulation modulation 1h + 526h 1h + 526h line kil h h ynrinv ynrlim ynrk cnrinv cnrlim cnrk nonstandard signal detection killer detection 7.1 ynr/cnr processing the frame difference ( ? y) signal is generated by subtracting the previous frame y signal from the current frame y signal. the noise component ? y' signal is extracted by eliminating the motion component of the ? y signal at the nonlinear filter. noise components are reduced by subtracting the noise component ? y' signal from the current frame y signal. at the same time, the y signal submitted to noise reduction is delayed by a frame to be used to generate ? y for the next frame. this way the frame recursive ynr is configured. much the same processing is performed for the c signal to reduce noise components. 7.2 nonlinear filter the ? y' and ? c' noise components are extracted from ? y and ? c. ? y and ? c contain inter-frame motion components and noise components. subtracting ? y and ? c from the current frame y and c signals causes inter-frame motion components to remain in the output picture. to solve this problem, a nonlinear filter that passes only low- amplitude signals is used; generally, motion components have a large amplitude, while noise components have a small amplitude. how nonlinear the filter is to be is specified using ynrk, ynrlim, ynrinv, cnrk, cnrlim, and cnrinv on the serial bus. 7.3 ynr/cnr operation stop if the nonstandard signal detection circuit detects a vertical nonstandard signal or frame sync nonstandard signal, or the line pin is at a high level, the killer detection circuit detects a color killer signal, or the kil pin is at a high level, ynr and cnr operations are stopped. free datasheet http://www.0pdf.com
pD64084 22 data sheet s16021ej2v0ds 8. nonstandard signal detection block this block detects nonstandard signals not conforming to the ntsc standard, such as vcr playback signals, home tv game signals, and laser-disc special playback signals. the detection result is used to stop inter-frame video processing. (and selects intra-field video processing forcibly.) figure 8-1. nonstandard signal detection block diagram video signal input h: nonstandard signal detected read register forced standard or nonstandard signal control inter-frame processing control signal to stop using ynr, cnr, and frame comb filter sync separation f sc trap hv counter noise level detection mixer frame sync nonstandard signal detection vertical sync nonstandard signal detection horizontal sync nonstandard signal detection line nstd vtrh vtrr ldsr ovsdf ohsdf nsds ldsdf wsc wss wsl coring 8.1 horizontal sync nonstandard signal detection the horizontal sync nonstandard signal detection circuit detects signals not having a standard relationship between f sc and f h (f sc = 227.5f h ) like a vcr playback signal. the sensitivity of detection is set using vtrr and vtrh on the serial bus. if the circuit detects a nonstandard signal, it stops using the frame comb filter. the detection result can be read using ohsdf on the serial bus. 8.2 vertical sync nonstandard signal detection the vertical sync nonstandard signal detection circuit detects signals not having a standard relationship between f h and f v (f h = 262.5f v ) like a vcr special playback signal and home tv game signal. the sensitivity of detection cannot be set. if the circuit detects a nonstandard signal, it stops using the frame comb filter, ynr, and cnr. the detection result can be read using ovsdf on the serial bus. 8.3 frame sync nonstandard signal detection the frame sync nonstandard signal detection circuit detects signals out of horizontal sync phase between frames, such as a laser-disc special playback signal. the sensitivity of detection is set using ldsr on the serial bus. if the circuit detects a nonstandard signal, it stops using the frame comb filter, ynr, and cnr. the detection result can be read using ldsdf on the serial bus. 8.4 forced standard or nonstandard signal control it is possible to specify either forced standard or nonstandard signal control using nsds on the serial bus. 8.5 noise level detection the noise level detection circuit detects a noise level in the flat portion of a video signal. the sensitivity of detection is set using wscor on the serial bus. the detection result can be read using wsl on the serial bus; it is not used in the ic. the detection result can be processed in a microprocessor to find a weak electric field. free datasheet http://www.0pdf.com
pD64084 23 data sheet s16021ej2v0ds 9. wcv-id decoder / id-1 decoder block this block decodes id-1 signal of 20h/283h and an identification control signal superimposed on a wide clear vision signal of 22h and 285h (the wide clear vision standard applies only in japan). 9.1 wcv-id decoder the wcv-id decoder checks whether the video signal contains an id signal by examining mainly the following seven items. if all these items turn out to be normal, an id signal is detected. the check and decode results are output to the ed2 bit and bits b3 to b17 on the serial bus, respectively. in addition, the phase of the confirmation signal is detected. <1> a difference in dc level between b1 and b2 is not smaller than a certain value. <2> the dc level of the sch part is not higher than a certain value. <3> the f sc amplitude of the nrz part is not larger than a certain value. <4> the f sc amplitude of the sch part is not smaller than a certain value (if fscoff = 0), <5> items <1> to <4> continue for at least 12 fields. <6> the parity of the nrz part (b3 to b5) is normal. note <7> the crc of the nrz part and sch part (b3 to b23) is normal. note note if an error is detected in item <6> or <7>, bits b3 to b17 on the serial bus hold the decoded value for the previous field. figure 9-1. wide clear vision id signal configuration ed2 bit (0: no id signal, 1: id signal) nrz part sch part crc code confirmation signal msb sa02 1 color burst b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 00 lsb msb sa03 lsb free datasheet http://www.0pdf.com
pD64084 24 data sheet s16021ej2v0ds 9.2 id-1 decoder the id-1 decoder checks whether the video signal contains an id-1 signal by examining mainly the following five items. if all these items turn out to be normal, an id signal is detected. <1> a difference of dc level between ref signal and the pedestal level is not smaller than a certain value. <2> the width of each bit is not smaller than a certain value. <3> items <1> to <2> continue for at least 6 fields. (when felchk register is set to zero, this check is disable) <4> crc check is passed. remark if any errors are detected in item <1> to <3>, the output for serial bus hold the decoded value for the previous field. if item <3> is disabled by setting felchk register to zero, crc check is also disabled. if any errors are detected by crc check, the output for serial bus will be initialized. initial values of serial bus registers are word0 = 00, word1 = 1111, word2 = 00h. figure 9-2. id-1 signal configuration crc code word2 word1 msb sa04 1 color burst b1 ref b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b20 b19 0 lsb msb sa05 lsb word0 free datasheet http://www.0pdf.com
pD64084 25 data sheet s16021ej2v0ds 10. y signal output processing block after y/c separation or y noise reduction, this block performs high-frequency coring, peaking, and vertical aperture compensation for the y signal submitted to ynr processing. figure 10-1. y signal output processing block diagram hpf ypft ypfg yhcor yhcgain id1on yaps0 yaps1 id1enw0a1 id1enw0a2 lpf bpf coring coring coring limiter 0 1 1 0 1 0 2 20/283h y y signal output (to the dtco pin) y signal output (to the y-dac pin) y high-frequency coring circuit id-1 encoder y peaking filter circuit vertical aperture compensation circuit vertical high-frequency component y high- frequency y low-frequency k line comb filter y/c separation hh decoding ynr vapinv 1 vapgain k composite input peaking component + vertical aperture conpensation component 10.1 y high-frequency coring circuit the y high-frequency coring circuit performs coring for the high-frequency component of the y main line signal. it works as a simplified noise reducer, because it can eliminate high-frequency components at 1 lsb to 3 lsb levels. the coring level is set using yhcor on the serial bus. <1> hpf circuit : separates the input y signal into the low- and high-frequency components. <2> coring circuit : performs coring for y high-frequency components according to the yhcor setting, and outputs a y signal by adding the y high- and low-frequency components after they are submitted to coring. the coring effect can set 1/2 times by the yhcgain setting. free datasheet http://www.0pdf.com
pD64084 26 data sheet s16021ej2v0ds 10.2 y peaking filter circuit the y peaking filter circuit performs peaking processing for the y signal to correct the frequency response of the y signal. <1> bpf circuit : extracts high-frequency components from the original y signal according to the ypft setting on the serial bus. the center frequency of the bpf can be selected from 3.58, 3.86, 4.08, and 4.22 mhz. <2> coring circuit : performs 2lsb (in 8-bit terms) coring for y high-frequency components to prevent s/n deterioration during peaking processing. <3> gain adjustment circuit : performs gain adjustment for peaking components according to the ypfg setting on the serial bus. the gain to be added can be changed in 16 steps over a range between ? 1.000 times and +0.875 times. <4> addition to the main line : y peaking components, together with vertical aperture compensation components, are added to the y signal. 10.3 vertical aperture compensation circuit the vertical aperture compensation circuit extracts vertical contour components from a y signal and adds them to the y signal to emphasize contours. <1> line comb filter : extracts vertical high-frequency components from the video signal. <2> lpf circuit : eliminates c signal components and y signal slant components to extract vertical contour components. <3> coring circuit : performs 1lsb (in 8-bit terms) coring for vertical high-frequency components to prevent s/n deterioration during aperture compensation. <4> gain adjustment circuit : performs gain adjustment for aperture compensation components according to the vapgain setting on the serial bus. <5> limiter circuit (nonlinear processing) : performs limit processing for aperture compensation components according to the vapinv setting on the serial bus. signals for which contours are to be emphasized are rather weak ones. uniform emphasis would result in initially large signals becoming too large. to solve this problem, the limiter circuit blocks signals larger than the vapinv setting, thereby disabling contour emphasis for large signals. <6> addition to the main line : vertical aperture compensation components, together with y peaking components, are added to the y signal. 10.4 turning on/off y peaking and vertical aperture compensation the yaps setting on the serial bus can be used to turn y peaking and vertical aperture compensation on and off. 10.5 id-1 encoder bit information conforming to the id-1 standard (cpx-1204) can be superimposed on the y signal output at 20h/283h. id1enon on the serial bus specifies whether to turn on or off superimposition. id1enw0a1 and id1enw0a2 specify the bit information to be superimposed. if id-1 information has already be superimposed on the original signal, it will be replaced with the newly specified id-1 information. free datasheet http://www.0pdf.com
pD64084 27 data sheet s16021ej2v0ds 11. c signal output processing block after y/c separation, the c signal output processing block performs delay adjustment, bpf processing, and gain adjustment for the c signal submitted to cnr processing. figure 11-1. c signal output processing block diagram couts1 2 couts0 bpf (f sc ) variable delay ( ? 0~ ? 7) cdl c signal output c signal input 11.1 c signal delay adjustment the delay time of the c signal can be varied in a range between 0 and 7 clock pulses (4f sc ) according to cdl on the serial bus. this way, the delay of the c signal relative to the y signal can be set to anywhere between ? 4 clock pulses ( ? 280 ns) and +3 clock pulses (+210 ns). 11.2 bpf and gain processing couts on the serial bus can be used to specify whether to insert a bpf. it can also be used to specify the gain ( 2 or 1). free datasheet http://www.0pdf.com
pD64084 28 data sheet s16021ej2v0ds 12. video signal output block the video signal output block can convert digital video signals to analog form. it can also output digital video signals without performing d/a conversion. figure 12-1. video signal output block diagram agnd avdd cbpy altf dyco ayo aco cbpc 2ch 10-bit dac (z ? 1 ) clk system clock (4f sc ) 4f sc ,910f h c signal input supply voltage analog y output digital yc / alternate flag output analog c output supply voltage 2.5 v for analog block c signal output processing y signal input y signal output processing 10 10 dycos1 f 0.1 f 0.1 f 0.1 f 10 12.1 digital yc output processing when setting up dycos = 00 on the serial bus, dyco9 (msb) to dyco0 (lsb) pins alternately output 10 bits of y signals in straight binary and 10 bits of c signals in offset binary. and altf pin outputs alternative flag of y or c signals. when altf = 'l' means "c signal outputs", when altf = 'h' means "y signal outputs". when setting up dycos = 1x on the serial bus, dyco9 (msb) to dyco0 (lsb) and altf pins are high-impedance. when the dyco pins are not used, setting dycos = 1x on the serial bus reduces radiation noise of these pins. when the external adc is used, dyco9 to dyco0 pins are used as the digital input terminal of video signal. so the digital yc output is not available. 12.2 video signal output level figure 12-2 shows sample waveforms that would be observed at the ayo and aco pins after a typical video signal is input (see 3. video signal input block ). free datasheet http://www.0pdf.com
pD64084 29 data sheet s16021ej2v0ds figure 12-2. video signal output waveform example (for 75 % color bar input) pedestal: 0 ire = 256 lsb sync-tip: ? 40 ire = 20 lsb 100 ire = 840 lsb max. 131 ire = 1023 lsb 1.94 v 0.94 v 140 ire p-p = 0.8 v p-p = 820 lsb center = 512 lsb couts = 0x couts = 1x burst: 40 ire p-p = 0.23 v p-p = 234 lsb max.: 175 ire p-p = 1 v p-p = 1023 lsb + 131 ire: 1023 896 768 640 512 384 0 ire: 256 128 ? 43 ire: 0 ire: dyco output (lsb) + 87 ire: 1023 896 768 640 0 ire: 512 384 256 128 ? 87 ire: 0 ire: dyco output (lsb) ayo output (v, typ.) 1.94 v 0.94 v aco output (v, typ.) 12.3 pin treatment ? supply 2.5 v to the avdd pins and supply 3.3 v to the dvddio pin. isolate them sufficiently from the digital section power supply. ? use as wide wiring patterns as possible as the ground lines of each bypass capacitor and the agnd pins so as to minimize their impedance. ? pull down the cbpy and cbpc pins via a 0.1 f bypass capacitor. ? when dac aren't used, connect agnd pin to digital ground, avdd pin to digital power supply, and ayo, aco, cbpy and cbpc pins set open. ? when the digital i/o pin dyco9 to dyco0 aren't used, these pins set open. free datasheet http://www.0pdf.com
pD64084 30 data sheet s16021ej2v0ds 13. extend digital input / output this device have the extend digital i/o terminals extdyco9-extdyco0 in addition to dyco9-dyco0. using these terminals, the digital in to digital out system is available. table 13-1. mode setting for extend digital i/o terminals serial bus condition of each terminals extdyco exadins dycos[1] dycon extdycon altf extaltf a/d d/a 000outlow note flag low on on 01xinlow note 4fsc low off on 001low note low note low low on on 100outlow note flag low on on 1 1 0 out in flag 4fsc off on 101low note out low flag on on 1 1 1 in out 4fsc flag off on note by setting hizen (sa16h, d4) = 1, these pin status are set to hi-z. 13.1 usage of extend digital i/o terminals the extended digital i/o pin extdyco9 to extdyco0 becomes effective by setting serial bus to extdyco = 1. at this time, internal adc can not be available. the i/o mode selection of extdyco9 to extdyco0 are set by serial bus dycos. when using input mode of dycon or extdycon pins, insert serial resistor in the lines. 13.2 digital yc output format the specification of the digital input and output for the extended digital i/o pin extdyco9 to extdyco0 is same as usual digital i/o pin dyco9 to dyco0. when using in input mode, input 10-bit digitized composite video signal that is sampled by 4fsc. and when using in output mode, extdyco9 (msb) to extdyco0 (lsb) pins alternately output 10 bits of y signals in straight binary and 10 bits of c signals in offset binary. and extaltf pin outputs alternative flag of y or c signals. when altf = 'l' means "c signal outputs", when altf = 'h' means "y signal outputs". the internal adc and extended digital i/o can ? t work at the same time. and extended digital i/o pins have 3.3 v resistant. 13.3 pin treatment ? when the extended digital i/o pin extdyco9 to extdyco0 aren't used, these pins set open. free datasheet http://www.0pdf.com
pD64084 31 data sheet s16021ej2v0ds 14. digital connection with ghost reducer ic pd64031a the pD64084 can perform processing from ghost reduction to three-dimension y/c separation digitally in 10-bit units when it is directly connected to nec electronics' ghost reducer ic pd64031a. figure 14-1 shows the system configuration when the pd64031a and pD64084 are digitally connected directly. 14.1 outline when signals are input from a ground wave tuner, the composite video signal is first input to the a/d converter of the pd64031a, where the ghost of the signal is reduced. the digital clamp circuit then adjusts the pedestal level, and the digital amplifier circuit adjusts the amplitude of the signal. as a result, a 10-bit digital composite video signal is sent to the three-dimension y/c separation ic pD64084. the pD64084 then performs processing such as y/c separation and outputs a y/c video signal that has been converted into an analog signal (see figure 14-1). figure 14-1. example of digital connection system with ghost reducer (when signals are input from tuner) do9 to do0 altf ocp cso delay c sync separation f sc bpf 1/2 adc dac dac wp1 clk8 ckmd dyco9 to dyco0 altf st0 csi clk8 ckmd xi xo fsco csi vin c20o fsci xi xo fsco fsci ayi ayo aco gr filter adc 8f sc pll f sc generator 8f sc pll f sc /227.5f h generator y/c separation digital clamp amplifier chroma signal burst flag burst flag 8f sc system clock 8f sc system clock y/c video output clamp pulse chroma, sync signal 4f sc f sc f sc path selection 8f sc 10-bit digital composite video signal 20 mhz tuner input composite video signal input clk8 input and 8f sc pl l stop pd64031a pD64084 free datasheet http://www.0pdf.com
pD64084 32 data sheet s16021ej2v0ds when signals are input from video (composite or s input), the pd64031a is not used, and the video signal is directly input to the a/d converter of the pD64084 (see figure 14-2). figure 14-2. example of digital connection system without ghost reducer (when signals are input from external source) do9 to do0 altf ocp cso delay c sync separation f sc bpf 1/2 adc dac dac wp1 clk8 ckmd altf st0 csi clk8 ckmd xi xo fsco csi vin c20o fsci xi xo fsco fsci ay i ayo aco gr filter adc 8f sc pll f sc generator 8f sc pll f sc /227.5f h generator y/c separation digital clamp amplifier chroma signal burst clamp burst clamp 8f sc system clock 8f sc system clock y/c video output clamp pulse chroma, sync signal 4f sc f sc 3dyc/gr selection 8f sc 10-bit digital composite video signal 20 mhz composite video signal input external pin input, etc. clk8 input and 8f sc pll stop dyco9 to dyco0 pd64031a pD64084 free datasheet http://www.0pdf.com
pD64084 33 data sheet s16021ej2v0ds 14.2 system configuration and control method 14.2.1 selecting video signal input path when a video signal is input from a tuner or external pin, the input path of the video signal must be selected. this selection is made by a serial bus register of the pD64084. if the signal is input from a tuner when the ghost reducer is used, a digital video signal input pin is selected by the pD64084. when signals are input from other external pins (such as those of a vcr, dvd, video camera, or game machine), the internal a/d converter of the pD64084 is made valid, so that the video signal directly input to the pD64084 becomes valid. for details on how to set the pins and registers, see table 14-1 and table 14-2 in section 14.3 . 14.2.2 selecting mode according to clock and video signal input path when the pd64031a and pD64084 are digitally connected directly, the system clock must be shared by the two ics. when the ghost reducer is used (when signals are input from a tuner), the pd64031a generates burst lock clock f sc , as shown in figure 14-1. this f sc goes through an external bpf and is input to the 8f sc pll of the pD64084, where system clocks (8f sc and 4f sc ) are generated. these system clocks are used by the pD64084, and are also supplied to the pd64031a by the pD64084 from the clk8 pin. when the ghost reducer is not used (when signals are input from an external source), the video signal is not input to the pd64031a, and only the pD64084 operates. it is therefore necessary that the burst clock generated by the pD64084 be used. to switch the path of inputting f sc to the f sc bpf between the fsco pin of the pd64031a and the fsco pin of the pD64084, an analog switch is necessary in the input block of the f sc bpf. this analog switch is controlled by the wp1 pin of the pd64031a. the wp1 pin is controlled by register dir3dyc (sa08h: d7 and d6) of the pd64031a (that selects a three-dimension y/c separation digital connection mode). by changing the setting of this register depending on whether the ghost reducer is used or not, the analog switch can be controlled by the signal output from the wp1 pin. in this way, the f sc path can be changed. a 20-mhz crystal oscillator that generates the basic clock for the f sc generator should be provided to the pd64031a. when the ghost reducer is not used and the pD64084 operates alone, the 20-mhz clock output from the c20o pin of the pd64031a is used. for details on how to set the pins and registers, see table 14-1 and table 14-2 in section 14.3 . free datasheet http://www.0pdf.com
pD64084 34 data sheet s16021ej2v0ds 14.3 setting of digital direct-connected system 14.3.1 hardware setting see the pin connection and setting in the following table to digitally connect the pd64031a and pD64084 directly. table 14-1. pin setting for digital direct-connection pd64031a pin signal direction pD64084 pin function do9 to do0 (pins 6 to 15) dyco0 to dyco9 (pins 63 to 72) 10-bit digital video signal interface n3d (pin 3) line (pin 74) three-dimension processing prohibiting flag register n3d1sten of the pd64031a (sa01h: d5) must be set. cso (pin 4) csi (pin 77) composite sync signal the signal from the sync separation circuit connected to the pd64031a is shared by the pD64084. altf (pin 5) altf (pin 73) digital clamp clock (4f sc ) register adclks of the pD64084 (sa15h: d7 and d6) must be set. ocp (pin 18) st0 (pin 59) clamp pulse for digital clamp circuit register st0s of the pD64084 (sa07h: d1 and d0) must be set. clk8 (pin 30) clk8 (pin 57) system clock (8f sc ) register clk8off of the pD64084 (sa07h: d4) must be set. fsco (pin 47) fsci (pin 54) burst lock clock (connected via an analog switch) c20o (pin 54) xi (pin 36) 20-mhz reference clock ckmd (pin 31) ?? fixed to high level (external clock mode) wp1 (pin 35) ?? connected to analog switch (control signal output) this pin is controlled by register dir3dyc of the pd64031a (sa08h: d7 and d6) to select a clock path. exdas (pin 58) ?? fixed to high level (digital output is valid) fsci (pin 40) ?? fixed to gnd (f sc generator is not used) ?? fsco (pin 51) connected to analog switch ?? xo (pin 37) open free datasheet http://www.0pdf.com
pD64084 35 data sheet s16021ej2v0ds 14.3.2 register setting correctly set the following registers when digitally connecting the pd64031a and pD64084 directly. also refer to the following table for register setting to specify whether the ghost reducer is used or not. table 14-2. register setting register with ghost reducer used with ghost reducer not used remark pd64031a exdas (sa01h: d7) 1 don ? t care digital data output setting n3d1sten (sa01h: d5) 1 don ? t care 3-dimesnion processing prohibiting flag setting clk20low (sa01h: d2) 0 don ? t care 20-mhz clock output setting adcpmd (sa04h: d5, d4) 10 adc input bias mode setting dir3dyc (sa08h: d7, d6) 10 11 mode selection (wp1 pin control) dcpag (sa08h: d5 to d3) 101 don ? t care digital clamp characteristic setting dcpen (sa09h: d6) 1 don ? t care digital clamp selection dcplpfs (sa09h: d5) 1 don ? t care error calculation block lpf selection dcpven (sa09h: d4) 1 don ? t care clamp timing setting dcp_test (sa09h: d3 to d0) 1111 don ? t care permissible error range during clamping pD64084 exadins (sa02h: d5) 1 0 internal adc selection clk8off (sa07h: d4) 0 8f sc output setting st0s (sa07h: d1, d0) 01 don ? t care clamp pulse output setting adclks (sa15h: d7, d6) 01 11 altf clock delay setting hizen (sa16h: d4) 1 digital input / output status select free datasheet http://www.0pdf.com
pD64084 36 data sheet s16021ej2v0ds 15. i 2 c bus interface 15.1 basic specification the i 2 c bus is a two-wire bi-directional serial bus developed by philips. it consists of a serial data line (sda) for communication between ics and a serial clock line (scl) for establishing sync in communication. figure 15-1. i 2 c bus interface serial data line master ic slave ic 3.3 v supply voltage serial clock line scl sda scl sda slave ic scl sda the following procedure is used to transfer data from the master ic to a slave ic. <1> start condition : to start communication, hold the scl at a high level, then pull down the sda from a high to a low level. <2> data transfer : to transfer data, pull up the scl from a low to a high, while holding the current state of the sda. data transfer is carried out in units of 9 bits, that is, 8 data bits (d7 to d0, msb first) plus an acknowledgment bit (ack). a selected slave ic sets the sda to a low when it receives bit 9 to send acknowledgment. <3> stop condition : to terminate communication, pull up the sda from a low to a high upon acknowledgment, while keeping the scl at a high. figure 15-2. start condition, data transfer, and stop condition formats start condition s 0.1 min. s 0.1 min. s 0.6 min. s 0.6 min. s 1.3 min. data acceptance scl sda (master) sda (slave) d7 d6 stop condition 0 ns min. d5 d4 d1 d0 ack ack hi-z d0 d7 s 0.6 min. hi-z free datasheet http://www.0pdf.com
pD64084 37 data sheet s16021ej2v0ds 15.2 data transfer formats immediately when the master ic satisfies the start condition, each slave receives a slave address. if the received slave address matches that of a slave ic, communication begins between the slave ic and the master ic. if not, the sda line is released. two sets of slave addresses can be specified according to the sla pin. table 15-1. slave address sla pin setting slave address (unchangeable when power is on) write mode read mode l or open b8h (1011 1000b) b9h (1011 1001b) h bah (1011 1010b) bbh (1011 1011b) (1) write mode formats (reception mode for slaves) if a slave ic receives its write-mode slave address in byte 1, it continues to receive a subaddress in byte 2 and data in the subsequent bytes. the subaddress auto-increment function enables continuous data reception. figure 15-3. write mode formats (a) one-byte write format start stop slave address w 1 bit 1 bit 8 bits 8 bits 1 bit 8 bits a a a sub address n data (sub address n) (b) multiple-byte write format start stop slave address w 1 bit 1 bit 8 bits 8 bits 1 bit 8 bits 1 bit 8 bits a a a a a sub address n data (sub address n) data (sub address n+1) 1 bit 1 bit 8 bits a data (sub address 17h) remark start : start condition stop : stop condition sr : restart condition w : write mode specification (= 0) r : read mode specification (= 1) a : acknowledgment n : no-acknowledgment xxx : master device xxx : slave device ( pD64084) free datasheet http://www.0pdf.com
pD64084 38 data sheet s16021ej2v0ds (2) read mode format (transmission mode for slaves) if a slave ic receives its read-mode slave address in byte 1, it sends data in byte 2 and the subsequent bytes. no subaddress is specified in this mode. transmission begins always at address 0. before establishing a stop condition, the master ic must send no-acknowledgment and release the sda line. figure 15-4. read mode format (a) single read format start stop slave address r 1 bit 1 bit 8 bits 8 bits 1 bit 8 bits 1 bit a a a a n data (sub address 0) data (sub address 1) 8 bits data (sub address n) (b) multiple read format start stop slave address sub address n r slave address w 1 bit 1 bit 8 bits 8 bits 1 bit 8 bits 1 bit 1 bit a sr n 8 bits data (sub address 06h) a a 1 bit 8 bits a data (sub address n) a remark start : start condition stop : stop condition sr : restart condition w : write mode specification (= 0) r : read mode specification (= 1) a : acknowledgment n : no-acknowledgment xxx : master device xxx : slave device ( pD64084) 15.3 initialization the serial bus registers are initialized when the pD64084 is reset (rstb). the i 2 c bus interface become operative after 100 s from reset operation. in addition, its write register is previously loaded with an initial value. for the reset operation, refer to 2.4 start-up of power supply and reset . free datasheet http://www.0pdf.com
pD64084 39 data sheet s16021ej2v0ds 15.4 serial bus registers the pD64084 incorporates twenty-four 8-bit write registers and seven 8-bit read registers. writing to the write registers is possible in the write mode (with a slave in reception mode), while reading from the read registers is possible in the read mode (with a slave in transmission mode). the following table lists how each serial bus register is mapped. (1) write register mapping slave address: 10111000b = b8h (sla0 = l), 10111010b = bah (sla0 = h) data map (sa00-sa17) sa d7 d6 d5 d4 d3 d2 d1 d0 00 0 nrmd 0 1 couts yaps 01 clks nsds mss kils 02 dycos exadins mfreeze pecs excss 03 0 cpp hdp cdl 04 dycor dygain 05 dccor dcgain 06 ynrk ynrinv ynrlim cnrk cnrinv cnrlim 07 id1on id1w0a1 id1w0a2 clk8off st1s st0s 08 wsc vtrh vtrr ldsr 09 wss id1decon th felchk tt vflth 0a vapgain vapinv 0b 0 0 ypft ypfg 0c v1psel vegsel cc3n c0hs clph seld2fh 0d00seld1fl00101 0e00001000 0f01000100 10 yhcor yhcgain ed2off ovst cshdt kctt 11 sht0 sht1 vct ott clkg2d clkggt clkgeb clkgt 12 hpllfs bpllfs fscfg pllfg kilr 13 hssl vssl 14 bgps bgpw 15 adclks adpds nsdsw nrzoff fscoff vtvh 16 syspds extdyco hizen vlsel vltype 0 0 17 cnrofs hcntfsyn adclpfsw adclpstp 0 0 0 0 caution it may be necessary to change set values on the serial bus depending on the results of performance evaluation conducted by nec electronics. free datasheet http://www.0pdf.com
pD64084 40 data sheet s16021ej2v0ds (2) read register mapping slave address: 10111001b = b9h (sla0 = l), 10111011b = bbh (sla0 = h) data map (sa00 - sa06) sa d7 d6 d5 d4 d3 d2 d1 d0 00 ver - kilf nsdf ldsdf ovsdf ohsdf 01 wsl 02ed2b3b4b5b6b7b8b9 03 b10 b11 b12 b13 b14 b15 b16 b17 04 - - id1w0 id1w1 05 id1w2 06 dclevh crcch dcfel crccfel hold1 - - - free datasheet http://www.0pdf.com
pD64084 41 data sheet s16021ej2v0ds 15.5 serial bus register functions table 15-2 lists the function of each write register. the initial and typical values for each register were determined for evaluation purposes by nec electronics. they are not necessarily optimum values. (1) write register table 15-2. write register functions (1/14) sa bit name and function description typical value initial value 00 d7 - undefined 0 0 d6 nrmd specifies an operation mode. 0 : ycs mode : y/c separation (burst locked clocking) y c 4f sc ycs (3d/2d) comp. memory adc dac dac 1 : ycs+ mode : 2d y/c separation and ynr/cnr (burst locked clocking) y c dac ynr cnr dac adc 4f sc ycs (2d) comp. memory -0 d5-d4 - undefined 01 01 d3-d2 couts specifies the way the c signal is output. (common to digital and analog outputs) 00: input-to-output gain of 2, without bpf processing 01: input-to-output gain of 2, with bpf processing 10: input-to-output gain of 1, without bpf processing 11: input-to-output gain of 1, with bpf processing 11 11 d1-d0 yap s specifies y signal output correction. (vertical aperture compensation and y peaking filtering) 00: correction is disabled for both analog and digital outputs. 01: correction is enabled for only analog outputs. 10: correction is enabled for only digital outputs. 11: correction is enabled for both analog and digital outputs. 11 11 free datasheet http://www.0pdf.com
pD64084 42 data sheet s16021ej2v0ds table 15-2. write register functions (2/14) sa bit name and function description typical value initial value 01 d7-d6 clks specifies whether to force use of the system clock. 00: automatic setting (in an operation mode specified by nrmd) 01: forced burst locked clocking 1x: forced line (horizontal) locked clocking caution if the specified setting does not match the input signal, a malfunction may occur. 00 00 d5-d4 nsds specifies whether to force standard/nonstandard signal processing. 00: adaptive processing (performed according to whether a nonstandard signal is detected) 01: forced standard signal processing (performed regardless of whether a nonstandard signal is detected) 10: forced horizontal sync nonstandard signal processing 11: forced vertical sync nonstandard signal processing (forced inter-line processing) caution if the specified setting does not match the input signal, a malfunction may occur. 00 00 d3-d2 mss specifies whether to force inter-frame or inter- line processing. 00: adaptive processing (performed according to the line pin input and motion detection signal) 01: forced inter-frame processing (performed according to the line pin input) 1x: forced inter-line processing 00 00 d1-d0 kils specifies whether to force killer processing 00: adaptive processing (performed according to the kil pin input and internal killer detection results) 01: internal killer detection is not used (processing is performed according to the kil pin input only). 1x: forced killer processing in killer processing, subtraction of the c signal from comp. signal is disabled. 01 01 free datasheet http://www.0pdf.com
pD64084 43 data sheet s16021ej2v0ds table 15-2. write register functions (3/14) sa bit name and function description typical value initial value 02 d7-d6 dycos specifies dyco pin input/output. in case of extdyco = 0 00: y/c separation signal alternate output 01: test mode (setting prohibited) 1x: low* high impedance in case of exdyco = 1 00: dyco9-0 : output, extdyco9-0 : input (when exadins=0, low note ) 01: test mode (setting prohibited) 1x: dyco9-0 : input (when exadins=0, low note ), extdyco9-0 : output note if hizen (sa16h, d4) = 1, then hi-z. 10 10 d5 exadins specifies whether to select external adc. 0: internal adc 1: external adc (digital video signal, converted from analog form, is input to the dyco9 to dyco0 pins) 00 d4 mfreeze external memory test bit 0: normal mode 1: test mode (setting prohibited) 00 d3-d2 pecs specifies a pedestal error correction test bit. 00: normal setting 01: test setting (setting prohibited) 10: test setting (setting prohibited) 11: test setting (setting prohibited) 00 00 d1-d0 excss specifies whether to use external c sync input. 00: internally separated sync signal is always used (csi input is not used). 01: sync signal input at the csi pin is used during out-of-sync state. 1x: sync signal input at the csi pin is always used. 01 01 03 d7 - undefined 0 0 d6 cpp specifies the clamp pulse width of internal adc 0 : 2.2 s 1 : 1.1 s 00 d5-d3 hdp fine adjustment of system horizontal phase 000: ? 1.12 s to 100: 0.00 s (typ.) to 111: +0.84 s fine-adjusts the horizontal-processing phase with respect to the horizontal sync signal (0.28 s/step). 100 100 d2-d0 cdl fine adjustment of c signal output delay 000: ? 280 ns to 100: 0 ns (typ.) to 111: +210 ns fine-adjusts the c signal phase with respect to the y signal (70 ns/step). 100 100 free datasheet http://www.0pdf.com
pD64084 44 data sheet s16021ej2v0ds table 15-2. write register functions (4/14) sa bit name and function description typical value initial value 04 d7-d4 dycor dy detection coring level (y motion detection coring) 0000: coring 0 (closer to motion pictures) to 1111: large amount of coring (closer to still pictures) the coring level for inter-frame y difference detection is specified. a signal smaller than specified is assumed to be noise, resulting in '0' being output. 0010 0010 d3-d0 dygain dy detection gain (y motion detection gain) 0000: gain of 0 (closer to still pictures) to 1111: maximum gain (closer to motion pictures) inter-frame y difference detection gain is specified. 1001 1001 05 d7-d4 dccor dc detection coring level (c motion detection coring) 0000: coring 0 (closer to motion pictures) to 1111: large amount of coring (closer to still pictures) the coring level for inter-frame c difference detection is specified. a signal smaller than specified is assumed to be noise, resulting in 0 being output. 0011 0011 d3-d0 dcgain dc detection gain (c motion detection gain) 0000: gain of 0 (closer to still pictures) to 1111: maximum gain (closer to motion pictures) inter-frame c difference detection gain is specified. 0110 0110 free datasheet http://www.0pdf.com
pD64084 45 data sheet s16021ej2v0ds table 15-2. write register functions (5/14) sa bit name and function description typical value initial value 06 d7 ynrk specifies the frame recursive ynr nonlinear filter gain. 0: x 6/8 (small noise reduction effect and small after-image) 1: x 7/8 (large noise reduction effect and large after-image) the magnitude of the nr effect is specified. 00 d6 ynrinv specifies the frame recursive ynr nonlinear filter convergence level. 0: 6 lsb (small noise reduction effect and small after-image) 1: 8 lsb (large noise reduction effect and large after-image) an input larger than specified is assumed to be a motion component, resulting in 0 being output. 00 d5-d4 ynrlim specifies the frame recursive ynr nonlinear filter limit level. 00: 0 lsb (ynr off) to 11: 3 lsb (large noise reduction effect and large after-image) an input larger than specified is assumed to be a motion component, resulting in a limit value being output. nonlinear characteristic curve based on ynrk, ynrinv, and ynrlim ? y' output (lsb) ? y input (lsb) ynrinv=1 ynrlim=3 ynrlim=2 ynrlim=1 ynrinv=0 4 ? 4 ? 8 3 ? 3 ? 6 2 ? 2 1 68 ? 1 ynrk=1 (k=7/8) ynrk=0 (k=6/8) remarks1. the characteristic are symmetrical with respect to the origin. 2. the levels shown are in 8-bit terms. 01 01 d3 cnrk specifies the frame recursive cnr nonlinear filter gain. 0: x 6/8 (small noise reduction effect and small after-image) 1: x 7/8 (large noise reduction effect and large after-image) the magnitude of the nr effect is specified. 00 d2 cnrinv specifies the frame recursive cnr nonlinear filter convergence level. 0: 6 lsb (small noise reduction effect and small after-image) 1: 8 lsb (large noise reduction effect and large after-image) an input larger than specified is assumed to be a motion component, resulting in 0 being output. 00 d1-d0 cnrlim specifies the frame recursive cnr nonlinear filter limit level. 00: 0 lsb (cnr off) to 11: 3 lsb (large noise reduction effect and large after-image) an input larger than specified is assumed to be a motion component, resulting in a limit value being output. nonlinear characteristic curve based on cnrk, cnrinv, and cnrlim ? c' output (lsb) ? c input (lsb) cnrinv=1 cnrlim=3 cnrlim=2 cnrlim=1 cnrinv=0 4 ? 4 ? 8 3 ? 3 ? 6 2 ? 2 1 68 ? 1 cnrk=1 (k=7/8) cnrk=0 (k=6/8) remarks1. the characteristic are symmetrical with respect to the origin. 2. the levels shown are in 8-bit terms. 01 01 free datasheet http://www.0pdf.com
pD64084 46 data sheet s16021ej2v0ds table 15-2. write register functions (6/14) sa bit name and function description typical value initial value 07 d7 id1enon specifies whether to superimpose id-1 specification id signal. 0: through (no superimposition) 1: forced superimposition caution do not set this bit to 1 during no-signal state. -0 d6 id1enw0a1 specifies whether to set bit a1 of id-1 word 0. 0: 0 (transmission aspect of 4:3) 1: 1 (transmission aspect of 16:9) -0 d5 id1enw0a2 specifies whether to set bit a2 of id-1 word 0. 0: 0 (image display format = normal) 1: 1 (image display format = letter box) -0 d4 clk8off specifies the state of the clk8 pin output. 0: active-low (to output 8f sc clock pulse) 1: fixed to low level (to reduce radiation noise) 10 d3-d2 st1s specifies internal signal monitor output for the st1 pin. 00: i 2 c sda inversed pulse 01: internal adc clamp pulse (active-high) 10: composite sync (active-low) 11: h sync (active-high) -00 d1-d0 st0s specifies internal signal monitor output for the st0 pin. 00: reserved 01: external adc clamp pulse (active-high) 10: hv blanking (active-high) 11: v sync (active-low) -00 free datasheet http://www.0pdf.com
pD64084 47 data sheet s16021ej2v0ds table 15-2. write register functions (7/14) sa bit name and function description typical value initial value 08 d7-d6 wsc specifies the amount of noise detection coring. 00: 0lsb (high detection sensitivity) 01: 1lsb 10: 2lsb 11: 3lsb (low detection sensitivity) specifies an input coring value for the noise detection circuit. detection results are not used within the device. 01 01 d5-d4 vtrh specifies hysteresis for horizontal sync nonstandard signal detection (out-of- horizontal sync intra-field) 00: hysteresis off (width of 0 clock pulses) 01: low hysteresis (width of 2 clock pulses) 10: medium hysteresis (width of 4 clock pulses) 11: high hysteresis (width of 6 clock pulses) for horizontal sync nonstandard signal detection, a criterion value to detect an out-of-horizontal sync state intra-field is decreased by a value indicated above. 01 01 d3-d2 vtrr specifies sensitivity for horizontal sync nonstandard signal detection (out-of- horizontal sync intra-field) 00: high detection sensitivity (width of 4 clock pulses) 01: medium detection sensitivity (width of 8 clock pulses) 10: low detection sensitivity (width of 12 clock pulses) 11: detection off if the degree of out-of-horizontal sync state intra-field becomes larger than specified, a horizontal sync nonstandard signal is assumed to have been detected. horizontal sync nonstandard signal detection characteristic curve standard-to-nonstandard hysteresis width standard-to-nonstandard decision criterion note 2 ohsd=1 (nonstandard signal detected) ohsd=0 (standard signal detected) vtrh 2(clk) note 1 (vtrr+1) 4(clk) note 1 notes 1. clk is in 4f sc units. 2. excluding when vtrr = 11 01 01 d1-d0 ldsr specifies sensitivity for frame sync nonstandard signal detection (out-of- horizontal sync inter- frame) 00: high detection sensitivity (width of 0.5 clock pulses) 01: medium detection sensitivity (width of 1 clock pulse) 10: low detection sensitivity (width of 1.5 clock pulses) 11: detection off if the degree of out-of-horizontal sync state inter-frame becomes larger than specified, a frame sync nonstandard signal is assumed to have been detected. 10 10 free datasheet http://www.0pdf.com
pD64084 48 data sheet s16021ej2v0ds table 15-2. write register functions (8/14) sa bit name and function description typical value initial value 09 d7 wss specifies the pre-filter characteristic of noise detection. 0 : normal ( pd64082 compatible) 1 : fsc trap 00 d6 id1decon id-1 decoder 0 : disable 1 : enable when decoding is disable, the output of register is following. word0=00, word1=1111, word2=00h 11 d5-d4 th id-1 decorder check level 01 : strict 00 : 10 : 11 : loose 00 00 d3 felchk id-1 decoder field check enable 0 : 6 fields check is disable 1 : 6 fields check is enable 11 d2-d1 tt id-1 decoder pulse width level 00 : 8clk 01 : 2clk 10 : 4clk 11 : 16clk 00 00 d0 vfilth specifies the vertical blanking (1h to 22h) bpf 0: bpf enable 1: bpf disable (through) 00 0a d7-d5 vapgain specifies a vertical aperture compensation gain. 000: correction off to 111: maximum correction (0.875 times) - 000 d4-d0 vapinv specifies a vertical aperture compensation convergence point. 00000: correction off to 11111: maximum correction vertical aperture compensation characteristic curve based on vapgain and vapinv input output vapinv ? vapinv tilt: vapgain/8 note tilt: fixed at ? 1 note the curve is symmetrical with resept to the origin coring: fixed at 1 - 00000 free datasheet http://www.0pdf.com
pD64084 49 data sheet s16021ej2v0ds table 15-2. write register functions (9/14) sa bit name and function description typical value initial value 0b d7 test te s t b i t 0: normal mode 1: test mode (setting prohibited) 00 d6 test te s t b i t 0: normal mode 1: test mode (setting prohibited) 00 d5-d4 ypft specifies the y peaking filter (bpf) center frequency. 00: 3.58 mhz, 01: 3.86 mhz, 10: 4.08 mhz, 11: 4.22 mhz y-peaking filter bpf characteristic curve gain f (mhz) k=0 k=1 k=2 k=3 1.25 1.13 1.00 0.88 0.75 0.63 0.50 0.38 0.25 0.13 0.00 0.89 1.79 2.68 3.58 4.47 5.37 6.26 7.16 11 11 d3-d0 ypfg specifies a y peaking filter gain. 0000: ? 1.0 times to 1000: 0.0 times to 1111: +0.875 times y signal output frequency characteristic curve based on ypft and ypfg 1.875 ypft=2 ypft=0 ypfg=15 ypfg=12 ypfg=8 ypfg=4 ypfg=0 output input freq. 1.5 1.0 0.5 0 0.5f sc f sc 1.5f sc 1000 1000 free datasheet http://www.0pdf.com
pD64084 50 data sheet s16021ej2v0ds table 15-2. write register functions (10/14) sa bit name and function description typical value initial value 0c d7-d6 v1psel line comb filter horizontal dot interference suppression level 00: suppression off 01: low suppression level 10: medium suppression level 11: high suppression level horizontal dot interference is reduced at inter-line y/c separation. 10 10 d5-d4 vegsel line comb filter vertical dot interference suppression level 00: suppression off 01: low suppression level 10: medium suppression level 11: high suppression level vertical dot interference is reduced at inter-line y/c separation. 10 10 d3 cc3n selects a line comb filter c separation filter characteristic. 0: narrow bandwidth 1: wide bandwidth 00 d2 c0hs specifies c signal delay time extension at nr 0: 1h delay 1: no 1h delay 00 d1 clph adc clamp test bit 0: normal mode 1: test mode (setting prohibited) 00 d0 seld2fh specifies dc detection high-frequency sensitivity. 0: low sensitivity, closer to still pictures 1: high sensitivity, closer to motion pictures 00 0d d7 - 0 0 0 d6 - 0 0 0 d5 seld1fl specifies dy detection low-frequency sensitivity. 0: low sensitivity, closer to still pictures 1: high sensitivity, closer to motion pictures 00 d4 - 0 0 0 d3 - 0 0 0 d2-d0 - 101 101 101 0e d7-d4 - 0000 0000 0000 d3-d0 - 1000 1000 1000 0f d7-d4 - 0100 0100 0100 d3-d0 - 0100 0100 0100 free datasheet http://www.0pdf.com
pD64084 51 data sheet s16021ej2v0ds table 15-2. write register functions (11/14) sa bit name and function description typical value initial value 10 d7-d6 yhcor specifies y output high frequency component coring. 00: coring off 01: small amount of coring (1 lsb: 8-bit terms) 10: medium amount of coring (2 lsb: 8-bit terms) 11: large amount of coring (3 lsb: 8-bit terms) coring characteristic curve (for high-frequency component only) remark converted into 8 bits input (lsb) ? yhcor yhcor output (lsb) solid line: yhcgain = 0 dotted line: yhcgain = 1 00 00 d5 yhcgain specifies y output high- frequency component coring gain. 0: normal ( 1) 1 :1/2 gain refer to yhcor (sa10h, d7-d6) 00 d4 ed2off specifies wcv-id detection circuit. 0: normal mode 1: forced wcv-id detection circuit turned off 00 d3 ovst nonstandard signal detection test bit 0: normal mode 1: test mode 00 d2 cshdt h / v counter test bit 0: normal mode 1: test mode 00 d1-d0 kctt h / v counter test bit 0x: normal mode 1x: test mode 00 00 free datasheet http://www.0pdf.com
pD64084 52 data sheet s16021ej2v0ds table 15-2. write register functions (12/14) sa bit name and function description typical value initial value 11 d7 sht1 nonstandard signal detection test bit 0: normal mode 1: test mode 00 d6 sht0 nonstandard signal detection test bit 0: normal mode 1: test mode 00 d5 vct h / v counter test bit 0: normal mode 1: test mode 00 d4 ott h / v counter test bit 0: normal mode 1: test mode 00 d3 clkg2d clock generator section test bit 0: test mode 1: normal mode 11 d2 clkggt clock generator section test bit 0: normal mode 1: test mode 00 d1 clkgeb clock generator section test bit 0: normal mode 1: test mode 00 d0 clkgt clock generator section test bit 0: normal mode 1: test mode 00 12 d7 hpllfs specifies the horizontal pll filter. 0: slow convergence 1: quick convergence -1 d6 bpllfs specifies the burst pll filter. 0: quick convergence 1: slow convergence 11 d5 fscfg specifies the burst extraction gain. 0: high gain 1: low gain 00 d4 pllfg specifies the pll loop gain. 0: low gain (slow convergence) 1: high gain (quick convergence) 11 d3-d0 kilr killer detection reference 0000: detection off 0001: low detection sensitivity to 1111: high detection sensitivity 0010 1010 13 d7-d4 hssl horizontal sync slice level 0000: 4lsb to 1111: 19lsb (in 8-bit input terms, 1lsb/step) 1111 1111 d3-d0 vssl vertical sync slice level 0000: hssl setting + 0lsb to 1111: hssl setting + 15lsb (in 8-bit input terms, 1lsb/step) 1000 1000 free datasheet http://www.0pdf.com
pD64084 53 data sheet s16021ej2v0ds table 15-2. write register functions (13/14) sa bit name and function description typical value initial value 14 d7-d4 bgps specifies the internal burst gate start position. 0000: h sync center + 2 s to 1111: h sync center + 5.75 s calculation of gate start position from the h sync center : 0.25 bgps + 2.0 ( s) 0101 0101 d3-d0 bgpw specifies the internal burst gate width. 0000: 0.5 s to 1111: 4.25 s calculation of gate width : 0.25 bgpw + 0.5 ( s) 0011 0011 15 d7-d6 adclks specifies the adc clock delay. 00: 0 ns typically (setting prohibited) 01: 3 ns typically 10: 17.5 ns typically 11: 20.5 ns typically 11 11 d5 adpds specifies whether to use adc power-down. 0: do not stop operation of adc not in use.( high current drain) 1: stop operation of adc not in use. (low current drain) 11 d4 nrdsw nonstandard detection section test 0: normal mode 1: test mode 00 d3 nrzoff wcv-id detection nrz section check 0: nrz section amplitude check on 1: nrz section amplitude check off 00 d2 fscoff wcv-id detection fsc section check 0: fsc amplitude check on 1: fsc amplitude check off 00 d1-d0 vtvh specifies wcv signal no- image section processing (only letter box signal is valid). 00: ordinary processing 01: forced inter-frame y/c separation 10: forced inter-line y/c separation 11: forced through (composite signal is output.) 00 00 free datasheet http://www.0pdf.com
pD64084 54 data sheet s16021ej2v0ds table 15-2. write register functions (14/14) sa bit name and function description typical value initial value 16 d7-d6 syspds system power down 00: normal operation 01: mode1 (d/a, memory access stop, total current :mid) 10: mode2 (memory access stop, total current: high 11: mode3 (a/d, d/a, memory access stop, total current : low) remark all register data are kept in power down term.reset is not required for re-start. 00 00 d5 extdyco extended digital i/o enable 0: extdyco9-extdyco0 disable 1: extdyco9-extdyco0 enable 00 d4 hizen digital input / output status select 0: low 1: hi-z 00 d3 vlsel te s t b i t 0: normal mode 1: test mode 00 d2 vltype te s t b i t 0: normal mode 1: test mode 00 d1 - undefined 0 0 d0 - undefined 0 0 17 d7 cnrofs cnr section test bit 0: normal mode 1: test mode 00 d6 hcntfsyn nonstandard signal detection test bit 0: normal mode 1: test mode (forced h counter synchronize) do not use ? 1 ? setting in the ycs mode. 00 d5 adclpfsw adc clamp test bit 0: normal mode 1: clamp level feedback disable 00 d4 adclpstp adc clamp test bit 0: normal mode 1: clamp disable 00 d3-d0 - undefined 0000 0000 free datasheet http://www.0pdf.com
pD64084 55 data sheet s16021ej2v0ds (2) read register table 15-3. read register functions (1/2) sa bit name and function description initial value 00 d7-d6 ver product version code version code of pD64084 is ? 01 ? (fixed) - d5 - undefined - d4 kilf killer detection flag 0: color signal detected 1: killer signal (non-burst signal) detected - d3 nsdf horizontal sync signal detection flag 0: sync signal detected 1: no sync signal detected - d2 ldsdf frame sync nonstandard signal detection flag 0: standard signal detected 1: nonstandard signal detected (such as laser disc special playback signal) - d1 ovsdf vertical sync nonstandard signal detection flag 0: standard signal detected 1: nonstandard signal detected (such as vcr special playback signal and home tv game signal) - d0 ohsdf horizontal sync nonstandard signal detection flag 0: standard signal detected 1: nonstandard signal detected (such as vcr ordinary playback signal) - 01 d7-d0 wsl noise level detection data 00000000: closer to low noise 11111111: closer to high noise - 02 d7 ed2 wcv-id signal detection flag 0: invalid (no wcv-id signal detected) 1: valid (wcv-id signal detected) - d6-d0 b3-b9 wcv-id signal decoding result - 03 d7-d0 b10-b17 wcv-id signal decoding result - 04 d7-d6 - undefined - d5-d4 id1w0 decoded data of id-1 word0 decoded data of word0 (2 bits) 00 d3-d0 id1w1 decoded data of id-1 word1 decoded data of word0 (4 bits) 1111 05 d7-d0 id1w1 decoded data of id-1 word2 decoded data of word0 (8 bits) 00h free datasheet http://www.0pdf.com
pD64084 56 data sheet s16021ej2v0ds table 14-3. read register functions (2/2) sa bit name and function description initial value 06 d7 dclevh id-1 decode reference signal detect 0 : reference signal is not detected 1 : reference signal is detected - d6 crcch id-1 decode crc check 0 : error 1 : normal - d5 dcfel id-1 decode reference signal field check 0 : error 1 : normal - d4 crccfel id-1 decode crc field check 0 : error 1 : normal - d3 hold1 id-1 decode signal availability check detection result 0 : error 1 : normal - d2-d0 - undefined - free datasheet http://www.0pdf.com
pD64084 57 data sheet s16021ej2v0ds 16. electrical characteristics absolute maximum ratings (t a = +25 c unless otherwise specified) parameter symbol conditions rating unit digital section supply voltage dv dd ? 0.3 to +3.6 v analog section supply voltage av dd ? 0.3 to +3.6 v dram section supply voltage dv ddram ? 0.3 to +3.6 v i/o section supply voltage dv ddio ? 0.3 to +4.6 v input voltage v i 3.3 v-resistant input pins ? 0.3 to +4.6 v output current i o ? 10 to +10 ma package allowable dissipation p d when mounted on an epoxy-glass board (t a = +70 c, 100 mm 100 mm, 2 layer, 1.6-mm thick) 964 mw operating ambient temperature t a device ambient temperature 0 to +70 c operating junction temperature t j:max upper limit to junction temperature +125 c storage temperature t stg ? 40 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions parameter symbol conditions min. typ. max. unit digital section supply voltage dv dd 2.3 2.5 2.7 v analog section supply voltage av dd 2.3 2.5 2.7 v dram section supply voltage dv ddram 2.3 2.5 2.7 v i/o section supply voltage dv ddio 3.0 3.3 3.6 v high-level input voltage v ih 3.3 v-resistant buffer 2.0 3.6 v low-level input voltage v il 00.8v high-level input voltage v ih schmitt input pin 0.7 dv ddio 3.6 v low-level input voltage v il 0 0.3 dv ddio v reference clock input frequency f xi xi pin 19.998 20.000 20.002 mhz reference clock input amplitude v xi 0.8 dv ddio v p-p subcarrier input frequency f fsci fsci pin 3.579545 mhz subcarrier input amplitude v fsci 0.45 av dd v p-p composite video signal input amplitude v ayi ayi pin, picture + sync. amp. (140 ire p-p ), av dd = 2.5 v 0.8 v p-p composite signal sync. signal input amplitude v ayi(s) ayi pin, sync. amp. (40 ire p-p ), av dd = 2.5 v 229 ( 0 db) 288 (+2 db) mv p-p free datasheet http://www.0pdf.com
pD64084 58 data sheet s16021ej2v0ds digital section dc characteristics (dv dd = dv ddram = 2.5 0.2 v, dv ddio = 3.3 0.3 v, dgnd = dgndram = 0 v, t a = 0 to +70c) parameter symbol conditions min. typ. max. unit digital section current drain di dd dvdd and dgnd pins 37 100 ma di ddram dvddram and dgndram pins 15 50 ma di ddio dvddio and dgnd pins 12 20 ma input leakage current i li ordinary input v i = dv ddio or 0 v ? 10 0+10 a high-level input current i ih pull-down type v i = dv ddio 20 83 200 a low-level input current i il pull-up type v i = 0 v ? 200 ? 83 ? 20 a high-level output current 1 i oh1 6.0 ma type v oh1 = 2.4 v ? 6.0 ma low-level output current 1 i ol1 v ol1 = 0.4 v +6.0 ma high-level output current 2 i oh2 3.0 ma type v oh2 = 2.4 v ? 2.0 ma low-level output current 2 i ol2 v ol2 = 0.4 v +3.0 ma low-level output current 3 i ol3 n-ch. open drain v ol3 = 0.4 v +6.0 ma output leakage current i lo 3-state, open drain v o = dv ddio to dgnd ? 10 0+10 a free datasheet http://www.0pdf.com
pD64084 59 data sheet s16021ej2v0ds analog section dc characteristics (av dd = 2.5 0.2 v, agnd = 0 v, t a = +25 c unless otherwise specified) parameter symbol conditions min. typ. max. unit analog section current drain ai dd avdd and agnd pins 50 100 ma adc resolution res ady -10-bit adc integral linearity error ile ady 3.0 6.0 lsb adc differential linearity error dle ady 1.0 2.0 lsb adc differential gain dg ady 2.0 3.0 % adc differential phase dp ady ayi pin, av dd = 2.5 v, f s = 4 f sc , dg ad , dp ad : ntsc 100 ire ramp 1.0 3.0 deg adc reference voltage(low) v rbady 0.75 v adc reference voltage(high) v rtady 1.25 v adc analog input range v inay 1.00 v adc clamp pin voltage v cly 0.70 v adc analog input capacitance c inad av dd = v in = 0 v, f in = 1 mhz 10 pf dac resolution res da -10-bit dac integral linearity error ile da 3.5 4.5 lsb dac differential linearity error dle da 0.5 1.0 lsb dac differential gain dg da 1.0 3.0 % dac differential phase dp da ayo and aco pins, av dd = 2.5 v, f s = 4f sc dg ad , dp ad : ntsc 100 ire ramp 1.0 3.0 deg dac full-scale output voltage v fsda 1.77 1.94 2.08 v dac zero-scale output voltage v zsda 0.77 0.94 1.07 v dac output amplitude v oppda ayo and aco pins, av dd = 2.5 v 1.00 v p-p f sc dac resolution res fsc fsco pin - 8 - bit free datasheet http://www.0pdf.com
pD64084 60 data sheet s16021ej2v0ds digital section ac characteristics (dv dd = dv ddram = 2.5 0.2 v, dv ddio = 3.3 0.3 v, dgnd = dgndram = 0 v, cl = 15 pf, t r = t f = 2 ns, t a = 0 to +70c) parameter symbol conditions min. typ. max. unit video data output delay t d:dat clk8 dycon, altf (exadins = 0) 3 9 20 ns internal signal monitor output delay t d:stat clk8 nstd, st1, st0 35 45 55 ns csi input set-up time t s:csi csi clk8 0ns csi input hold time t h:csi clk8 csi 15 ns altf output delay + dycon input set-up time t d:dyco-altf clk8 altf + : t s:dyco : exadins = 1, adclks = xx 35 ns altf output delay 0 t d:altf0 clk8 altf : exadins = 1, adclks = 00 323ns altf output delay 1 t d:altf1 clk8 altf : exadins = 1, adclks = 01 525ns altf output delay 2 t d:altf2 clk8 altf : exadins = 1, adclks = 10 18 38 ns altf output delay 3 t d:altf3 clk8 altf : exadins = 1, adclks = 11 20 40 ns dycon input set-up time t s:dyco dycon clk8 : exadins = 1 0ns dycon hold time t h:dyco clk8 dycon : exadins = 1 10 ns input capacitance c i dv dd = v i = 0 v, f in = 1 mhz 10 15 pf clk8 1/f clk8out t d:dat t d:altf t d:stat t h:dyco t s:dyco t d:dyco-altf altf (exadins=0) altf (exadins=1) dyco[9:0] (exadins=0) dyco[9:0] (exadins=1) hi-z hi-z nstd, st1, st0 t s:csi t h:csi csi (input) free datasheet http://www.0pdf.com
pD64084 61 data sheet s16021ej2v0ds clock and timing generation section ac characteristics (dv dd = dv ddram = av dd = 2.5 0.2 v, dv ddio = 3.3 0.3 v, dgnd = dgndram = agnd = 0 v, c l = 15 pf, t a = 0 to + 70c) parameter symbol conditions min. typ. max. unit subcarrier output frequency f fsco fsco pin 3.579545 mhz subcarrier output amplitude v fsco fsco pin, av dd = 3.3 v 1.00 v p-p clock output frequency f clk8out 28.63636 mhz clock output duty factor d clk8out clk8 pin, ckmd pin = dgnd, clk8off (sa07:d4) = 0 45 50 55 % f sc pull-in range (in f sc terms) f bp when the burst locked clock operation 600 hz horizontal sync attenuation (capture range) v hi ? 8 0db vertical sync attenuation (capture range) v vi sync input amplitude, hssl = 1111, vssl = 1000 (assumed to be 0db when inputting 40ire = 59lsb) ? 6 0db adc and dac section ac characteristics (av dd = 2.5 0.2 v, agnd = 0 v, c l = 15 pf, t a = +25 c) parameter symbol conditions min. typ. max. unit adc acquisition time note t ackad clk8 ay i 7ns dac setting time note t setda clk8 ayo, aco 15 ns note excluding data conversion delay clk8 t ackad ay i ayo, ac o t setda i 2 c bus interface section ac characteristics (dv dd = 2.5 0.2 v, dgnd = 0 v, c l = 15 pf, t a = 0 to +70 c) parameter symbol conditions min. typ. max. unit sda pin ack response delay t ack scl sda 500 ns sda data set-up time t su:dat sda:l scl 100 ns sda data hold time t hd:dat scl sda:hi-z 0ns t ack t su:dat t hd:dat sda (slave) scl (from master) hi-z 8th clock 9th clock 1st clock free datasheet http://www.0pdf.com
pD64084 62 data sheet s16021ej2v0ds 17. application circuit example kil line csi altf nstd st1 st0 clk8 ckmd dyco9-dyco0 test13-test17 open open test01-test12 test18-test26 dvddio internal memory dvddram 2 dgndram 2 testic1, testic2 killer input (option) forced 2d c-sync. input ext. adc clock digital y input non standard detection states 1 [hd, etc.] states 0 [vd, etc.] 8f sc clock output clock mode (gnd) i/o block power supply (3.3 v) f 0.1 pD64084 f 47 avdd vcomy avdd c-dac y- da c adc agnd cbpc aco ayo ay i vcly vrby cbpy agnd analog comp. input analog y output analog c output analog block power supply (2.5 v) vrty f 10 f 10 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 2 0.1 f 10 dvdd 3 0 ? sda scl sla0 avdd avdd dvdd dgnd dgnd 4 rpll fsci agnd agnd fsco xo xi i 2 c bus interface i 2 c bus interface 8f sc / 1820f h pll f sc / (455/2)f h generator digital block power supply (2.5 v) system reset rstb f 0.1 f 0.1 f 0.1 f 3 0.1 f 0.1 f 10 f 47 f 0.01 22~33 pf 20 mhz x'tal 22~33 pf bpf caution this application circuit and the circuit parameters are for reference only, and not intended for use in actual design-ins. free datasheet http://www.0pdf.com
pD64084 63 data sheet s16021ej2v0ds 18. package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h free datasheet http://www.0pdf.com
pD64084 64 data sheet s16021ej2v0ds 19. recommended soldering conditions the pD64084 should be solderd and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, content an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 19-1. surface mounting type soldering conditions ? ? ? ? pD64084gc-8ea-a note1 : 100-pin plastic lqfp (fine pitch) (14 14 mm) ? ? ? ? pD64084gc-8ea-y note2 : 100-pin plastic lqfp (fine pitch) (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c or below, time: 30 s. max. (at 210 c or higher), count: three times or less, exposure limit: 7 days note3 (after that, prebake at 125 c for 10 to 72 hours) products packed in a medium other than a heat-resistance tray (such as a magazine, taping, and non-heat-resistance tray) cannot be baked. ir60-107-3 partial heating pin temperature: 300 c max., time: 3 s. max. (per pin row) - notes 1. lead-free product 2. high-thermal-resistance product 3. after opening the dry pack, store it at 25 c or less and 65 % rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). free datasheet http://www.0pdf.com
pD64084 65 data sheet s16021ej2v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. free datasheet http://www.0pdf.com
pD64084 purchase of nec electronics l 2 c components conveys a license under the philips l 2 c patent rights to use these components in an l 2 c system, provided that the system conforms to the l 2 c standard specification as defined by philips. the information in this document is current as of march, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec e lectronics endeavors to enhance the quality, reliability and safety of nec e lectronics p roducts, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec e lectronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec e lectronics" as used in this statement means nec e lectronics c orporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": free datasheet http://www.0pdf.com

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